Engineering Resources
RF & Microwave Toolbox
Professional calculators and reference formulas for high-frequency hardware design.
RF model 2026.07-r2 · source 1723aee3
System Cascade Chain Builder
Interactive drag-and-drop block diagram for cascade Gain, Noise Figure, and OIP3/IIP3 analysis.
Components
System Results
Gain
7.00 dB
NF
1.99 dB
OIP3
10.24 dBm
IIP3
3.24 dBm
LNA
Filter
Mixer
Drag & Connect from left to right
Press enter or space to select a node. You can then use the arrow keys to move the node around. Press delete to remove it and escape to cancel.
Press enter or space to select an edge. You can then press delete to remove it or escape to cancel.
Receiver Link Budget
Evaluate detailed gain and noise figure requirements across an RF receiver front-end.
System Receiver Analysis (MDS & SFDR)
Closed-form approximationPerformance Metrics
Input-Referred Receiver Noise -97.49 dBm
Spurious-Free Dynamic Range (SFDR) 61.66 dB
Receiver Sensitivity -85.49 dBm
Uses −174 dBm/Hz at 290 K plus bandwidth and NF. SFDR=(2/3)(IIP3−noise) assumes two equal in-band interferers, third-order products, a 1 Hz-equivalent comparison convention, and no blockers, reciprocal mixing, compression, quantization, or phase-noise limit.
PLL Loop Filter Synthesis
Estimate 2nd order passive charge-pump PLL loop filters with explicit bandwidth and phase-margin assumptions.
PLL Loop Filter Synthesis (2nd Order Passive)
Closed-form approximationFilter Components
Shunt Capacitor (C1) 2.62 nF
Series Capacitor (C2) 12.67 nF
Series Resistor (R2) 303.38 Ω
Ideal Type-II, second-order charge-pump PLL synthesis using Kpd=Icp/(2π), Kvco in Hz/V, no extra pole, and the entered crossover/phase margin. Charge-pump output resistance, VCO input capacitance, leakage, delay, reference spurs, discrete component choices, and PVT are excluded; verify the implemented loop in a PLL simulator before tapeout or hardware release.