Engineering Resources

RF & Microwave Toolbox

Professional calculators and reference formulas for high-frequency hardware design.

RF model 2026.07-r2 · source 20d8de00

System Cascade Chain Builder

Interactive drag-and-drop block diagram for cascade Gain, Noise Figure, and OIP3/IIP3 analysis, with a live level diagram and noise and linearity budgets.

Parts

Click a part to append it to the chain, or drag from an output port to an input port.

React Flow

Signal flows left to right

Cascaded gain7.00dB
Noise figure1.99dB
Output IP310.24dBm
Input IP33.24dBm

Level diagram

Drive the chain and watch the margins move at every interface.

Output SNR32.0dB
SFDR63.5dB
Tightest headroom65.0dBAt the LNA output.
Signal Noise floor · 100 MHz Stage OIP3 Tightest headroom
dBm40200−20−40−60−80−100OIP3 20.0OIP3 100.0OIP3 15.065.0 dBheadroom−60.0−94.0−45.0−77.5−47.0−79.4−53.0−85.0SNR32.0 dB01 LNA+15.0 dB · cum NF 1.5002 Filter−2.0 dB · cum NF 1.5603 Mixer−6.0 dB · cum NF 1.99
Swipe the diagram sideways to see every stage.Matched-stage Friis lineup: the noise floor is kT₀B·F·G with kT₀ = −174 dBm/Hz (290 K), cascaded IP3 adds 1/IIP3 terms in phase (the worst case), and SFDR = ⅔(IIP3 − kT₀B − NF). Signal levels are small-signal, with no compression modeled. For a memoryless cubic nonlinearity the input P1dB sits 9.6 dB below IIP3, so a stage with under about 10 dB of OIP3 headroom is already near compression.

Noise budget

Share of F − 1 each stage adds
  1. 01LNA71.1 %
  2. 02Filter3.2 %
  3. 03Mixer25.7 %

Linearity budget

Share of 1 / IIP3 each stage adds
  1. 01LNA66.6 %
  2. 02Filter0.0 %
  3. 03Mixer33.4 %

Receiver Link Budget

Evaluate detailed gain and noise figure requirements across an RF receiver front-end.

System Receiver Analysis (MDS & SFDR)

Closed-form approximation
Performance Metrics
Input-Referred Receiver Noise -97.49 dBm
Spurious-Free Dynamic Range (SFDR) 61.66 dB
Receiver Sensitivity -85.49 dBm

Uses −174 dBm/Hz at 290 K plus bandwidth and NF. SFDR = (2/3)(IIP3 − N), with N the noise floor integrated over the stated bandwidth, is the range at which two equal in-band tones produce third-order products just at the floor; blockers, reciprocal mixing, compression, quantization, and phase-noise limits are excluded. Sensitivity adds the required SNR and the implementation loss to N.

PLL Loop Filter Synthesis

Estimate 2nd order passive charge-pump PLL loop filters with explicit bandwidth and phase-margin assumptions.

PLL Loop Filter Synthesis (2nd Order Passive)

Closed-form approximation
Filter Components
Shunt Capacitor (C1) 2.62 nF
Series Capacitor (C2) 12.67 nF
Series Resistor (R2) 303.38 Ω
Ideal Type-II, second-order charge-pump PLL synthesis using Kpd=Icp/(2π), Kvco in Hz/V, no extra pole, and the entered crossover/phase margin. Charge-pump output resistance, VCO input capacitance, leakage, delay, reference spurs, discrete component choices, and PVT are excluded; verify the implemented loop in a PLL simulator before tapeout or hardware release.